Floating gate memory devices such as flash memory devices typically utilize a metal oxide semiconductor field effect transistor (MOSFET) having an added, isolated, floating gate between the control gate and the MOSFET channel. During programming, a charge is placed on the floating gate to change the threshold voltage (Vt) of the transistor. To read the contents of the cell, a voltage level may be placed on the control gate between the expected Vt values for different levels of charge, and the value stored in the cell may be determined by whether or not the transistor conducts. Traditionally, flash memory devices stored a single bit per cell (called single-level cells or SLC). Many modern flash memory devices use multi-level cell (MLC) technology where multiple bits are stored in a single floating gate MOSFET, sometimes called a cell, by storing differing amounts of charge on the floating gate. The cell is programmed by biasing it with a voltage pulse followed by a verification pulse to read back the contents of the cell to determine if the threshold level (Vt) of the cell has increased to the desired level. If it hasn't, another programming pulse may be sent to the cell with a higher voltage followed by another verify cycle. This repeats until the cell has the desired Vt.
Many flash memory devices include extra bits of information that are used to hold error correction code (ECC) bits because some cells may be defective for some reason such as losing their charge at a very high rate, rendering them useless for long term non-volatile memory purposes. By storing ECC bits along with the data, data from some number of bad cells may be recovered, allowing for much higher device yields.
However, even good cells may experience charge change immediately after programming. In such a situation, milliseconds of time may elapse before the electrons that were trapped in the oxide layers around the floating gate to migrate to a stable location. Once the electrons have reached a final stable state, the cell is said to have reached charge equilibrium. Because it can take a long time for the cell to reach charge equilibrium, the verify cycle is usually performed long before charge equilibrium is reached. Quick Charge Gain (QCG) may refer to the condition where charge on the floating gate increases for some time after the programming pulse. In this case, Vt may be lower than its long term state when the verify cycle reads the cell This situation may lead to an extra programming pulse being applied to the cell, thereby causing the cell to be overcharged over the long term. Quick Charge Loss (QGL) may refer to the condition where charge on the floating gate decreases for some time after the programming pulse. In such a case, Vt may be higher than its long term state when the verify cycle reads the cell which may lead to the cell not receiving another programming pulse. As a result, the cell may be undercharged over the long term. To compensate for these effects, the target Vt distribution may be enlarged in order to accommodate all possible threshold voltages for a given state.
It will be appreciated that for simplicity and/or clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, if considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and/or analogous elements.